In recent years, there has been a strong demand for high-speed and low power consumption semiconductor integrated circuits. In order to realize high-speed semiconductor integrated circuits, it is well known that in addition to making semiconductor circuits with finer detail and making a gate length of a MIS (Metal Insulated Semiconductor) transistor or MOS (Metal Oxide Semiconductor) transistor short, it is extremely effective to lower a threshold voltage.
However, when the threshold voltage is set too low, there is a problem that power consumed by the semiconductor integrated circuit becomes extremely large because of the increase in a sub threshold leakage current that is unnecessary current flowing between the source and drain of a MOS transistor.
In the related art, a method of making substrate potentials (Vbp) of P-channel MOS transistors and substrate potentials (Vbn) of N-channel MOS transistors common, respectively, increasing a potential difference (power supply voltage) between a high-potential side potential (Vdd) and a low potential side potential (Vss) at high-speed cells, and reducing a power supply voltage at low power cells, is well-known (for example, refer to FIG. 1 of patent document 1).
Namely, the threshold voltage is set to a small value by applying a large power supply voltage to a high-speed cell and applying a voltage to a substrate bias in a forward direction. Further, the threshold voltage is set to a large value by applying a small power supply voltage to low power cells and applying a voltage to a substrate bias in a reverse direction.
Moreover, it is also well-known that a level shift circuit is provided between circuits in order to amplify the output amplitude of the transmitting side circuit so as to exceed the switching voltage of the receiving side circuit and prevent a penetration current of the receiving side circuit, when a signal is transmitted from a logic circuit having a small power supply voltage to a logic circuit having a large power supply voltage (patent document 1).    Patent Document 1: Japanese Patent Application Laid-Open No. 2001-332695.